Sr ASIC & FPGA Verification Engineer    

Location:
Phoenix, AZ ​​

RESPONSIBILITIES:

Sr Level Experience with UVM/SV testbench environments:

1) writing & debugging testbench components ( ie environments, configuration controls, subscriber units, agents, drivers, monitors, sequencers, sequences, and base tests),

2) writing tests, assertions, and functional coverage,

3) RTL Debug using UVM/SV testbench environment.  Preferably in a Mentor tool environment.

REQUIREMENTS:

10+ years ASIC & FPGA Verification - UVM/SV experience preferred.

​​Applicants selected may be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

​​Position ID:
CxD09AZ10

Contact: 
rose@cxd.com
CxDesign LLC
10645 N Tatum Blvd Suite 200

480-557-7111 X3

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